Semiconductor products are being fabricated with integrated memory and logic regions to an increasing extent. However, this makes particularly stringent requirements of the fabrication process, since different requirements are made of the field-effect transistors (FE transistors) in the memory and logic regions. Thus, by way of example, the FE transistors in the memory region, which generally serve there as selection transistors for assigned memory cells, must have a particularly low leakage current. By contrast, in the case of FE transistors in the logic region, particular importance is attached to a high switching speed and a low threshold voltage. In order to meet these different requirements, different, specially adapted fabrication methods have been developed for FE transistors for logic and memory applications.
One difference in fabrication resides e.g. in the fact that logic applications require complementary FE transistors, so-called CMOS transistors, in which, depending on the p- or n-channel, the gate material is also doped differently. In memory applications, only one gate material with one doping is generally used. The consequence of this is that only one channel, typically the n-channel, can be realized as surface channel, while the other channel, typically the p-channel, is realized as a so-called “buried channel”. In the course of further miniaturization, the “buried channel” has proved to have limited performance, so that nowadays, for this reason inter alia, in a logic process n- and p-type transistors are used as surface transistors and a higher performance can be obtained in this case. N-and p-channel transistors with a differently doped gate electrode or with gate materials with a different work function for electrons are also referred to as “dual work function devices” or “dual-gate devices”, generally the gate electrode of the n-channel transistor being n-doped and the gate electrode of the p-channel transistor being p-doped. The term dual work function is used hereinafter. A fabrication method suitable for fabricating transistors of this type is described for example in U.S. Pat. No. 5,882,965.
In order to set the different threshold voltages in logic and memory transistors, the gate dielectrics of the transistors are often formed with different thicknesses. A method in this respect is disclosed e.g. in U.S. Pat. No. 5,668,035, in which firstly a thick gate dielectric and a polysilicon layer are deposited on a silicon substrate both in the logic region and in the memory region and then both layers are removed from the logic region, where a comparatively thin gate dielectric is formed and a polysilicon layer is deposited. What is thereby achieved is that a thinner gate dielectric compared with the memory region is present in the logic region. The gate stack and also the source and drain regions are subsequently formed together both in the logic region and in the memory region.
By contrast, the formation of FE transistors for memory applications and dual work function transistors for logic applications on a common semiconductor substrate is described in U.S. Pat. No. 6,107,154, U.S. Pat. No. 6,153,459 and U.S. Pat. No. 6,087,225.
In the case of the method according to U.S. Pat. No. 6,107,154, firstly a gate oxide and a polysilicon layer are deposited onto a semiconductor substrate and subsequently patterned. In this case, gate electrodes of FE transistors are produced both in the logic region and in the memory region. This is followed by the simultaneous formation of source and drain regions in both regions. What is disadvantageous here is that the simultaneous fabrication of the FE transistors in both regions means that it is not possible to deal with the specific requirements of the FE transistors provided for logic and memory applications.
By contrast, U.S. Pat. No. 6,153,459 discloses patterning the gate oxide, deposited over the whole area of the semiconductor substrate, and the polysilicon layer, likewise deposited over the whole area, only in the memory region, whilst completely removing them in the logic region. Afterward, in the logic region, a gate oxide is formed and a polysilicon layer is deposited, said polysilicon layer being patterned only in the logic region with the formation of gate electrodes, whilst being completely removed in the memory region. The gate electrodes in the logic region are then n- or p-doped. Finally, the source and drain regions are formed in both regions.
By contrast, U.S. Pat. No. 6,087,225 describes the formation of a gate oxide and a first polysilicon layer in the memory region, formation of a gate oxide in the logic region and whole-area deposition of a second polysilicon layer with subsequent patterning, during which gate electrodes are formed in the logic region and the second polysilicon layer is removed in the memory region, and subsequent patterning of the first polysilicon layer for the formation of gate electrodes in the memory region. This is followed by the fabrication of source and drain regions both in the memory region and in the logic region.
What is disadvantageous about the previously known methods is that the method steps for fabricating the FE transistors in the memory or logic region have effects on the respective other region.